1. Field of the Invention
The present invention relates to a waveform digitizer apparatus using an interleaving AD conversion technique. More particularly, the present invention relates to a correction means that detects and corrects a measurement error caused by phase errors between sampling timings in interleaving AD conversion. Further, the present invention also relates to a Japanese patent application No. 2000-260271 filed on the date of Aug. 30, 2000, the contents of which are incorporated herein by reference.
2. Description of the Related Art
A waveform digitizer apparatus using an N-way interleaving AD conversion method uses NAD converters so as to increase a seeming sampling rate. Also, it is necessary to perform sampling at precise timings.
An example where two-way interleaving is performed is described below. In this example, the number of time-series data units is 212=4096. The waveform digitizer includes two AD converters, a window function multiplier, and an FT processor. The AD converter converts an analog signal to a digital signal at a fixed sampling rate. The two AD converters alternately sample the analog signal, thereby increasing the seeming sampling rate. The window function multiplier extracts data of the digital signal thus converted by the AD converter, the extracted data being data in a predetermined time domain. The window function multiplier multiplies the digital data by values obtained, at constant time intervals, from a predetermined function including a time axis. The window function multiplier multiplies the digital data by zero in the outside of the predetermined time region, thereby extracting the data in the predetermined time domain. In this example, the data extracted by the window function multiplier is a sequence of 4096 data units. The FT processor performs Fourier Transform for the digital signal extracted by the window function multiplier.
The FT processor receives the digital signal data sequence extracted by the window function multiplier and then outputs frequency spectra data formed by 4096 data units that have been subjected to Fast Fourier Transform. The FT processor includes the first FFT unit, the second FFT unit and a butterfly operation unit. Each of the first and second FFT units receives 2048 time-sequence data units and outputs 2048 intermediate data units (complex data units). The butterfly operation unit performs a butterfly operation that is the last one of known butterfly operations used in the FFT operation.
The butterfly operation unit performs the butterfly operation for the data sequences from the first and second FFT units and outputs the frequency spectra data of 4096 points obtained by the known butterfly operations applied in the FFT operation.
As an exemplary structure of a waveform digitizer in a semiconductor testing apparatus, a digitizer is known that includes the first and second AD converters to which an analog signal from a device under test is sent, an arranging unit and an FT processor. The first and second AD converters are completely the same in the sampling characteristics for performing AD conversion, including group delay characteristics and aperture delay characteristics. Typically, the sampled data sampled by the AD converters is temporarily stored in a buffer memory and is then supplied to the FT processor where the sampled data is subjected to the operation.
The analog signal for measurement that was output from the device under test is supplied to input ends of both the first and second AD converters. The first AD converter samples a sequence of even-numbered data units, so that it outputs a time series of the even-numbered time series data units, D0, D2, D4, . . . The second AD converter samples odd-numbered data units, so that it outputs a time series of the odd-numbered data units, D1, D3, D5, . . . The arranging unit receives both time series data and outputs a time series of data units obtained by alternately arranging the data units of both time series, D0, D1, D2, D3, D4, D5, . . .
The phase intervals of the sampling times of the two AD converters have to be adjusted in such a manner that the phase interval of the sampling times of one of the AD converters is equal to that of the other AD converter. Even in a case where there is an error in the phase intervals, the FFT operation is performed while considering the data units for which the FFT operation is to be performed as data units sampled at regular intervals. Therefore, correct frequency spectra cannot be obtained. Moreover, the coefficient of the multiplication by the window function multiplier is determined considering the data units to be multiplied by the coefficient as data units sampled at regular intervals. Therefore, the frequency spectra obtained by the FFT operation includes an error.
As described above, it was assumed in the conventional technique that the sampling timings did not change between a plurality of AD converters and the sampling clock rate was constant or within an acceptable error range. On the other hand, the sampling characteristics of the AD converter are affected by variation of parts of the AD converter, the environmental temperature, the change with the time and the change in the power source voltage, so that the sampling at regular intervals is affected. Moreover, in an application such as a semiconductor testing apparatus, in which the measurement is performed while the sampling frequency is changed, the group delay characteristics changes with the change of the sampling frequency. With these factors, the sampling timing is changed from the ideal sampling timing. This is not preferable in a case of obtaining the frequency spectra of the input signal with high precision and is therefore the practical problem.
Therefore, it is an object of the present invention to provide an interleaving AD conversion type digitizer apparatus and a semiconductor testing apparatus which can detect a sampling phase error between a plurality of AD converters and can correct operations performed by a window function multiplier and an FT processor. The above and other objects can be achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to the first aspect of the present invention, a digitizer apparatus comprises: NA/D converters operable to convert an analog signal output from a semiconductor device to digital signals at different sampling timings, respectively, where N is an integer equal to or larger than two; a window function multiplier operable to multiply the digital signals by predetermined correction coefficients, respectively; and an FT processor operable to perform Fourier Transform (FT) for the digital signals multiplied by the predetermined correction coefficients, wherein the window function multiplier multiplies the digital signals by the correction coefficients based on the sampling timings.
The N A/D converters may sample the analog signals at substantially the same frequency, and the window function multiplier may multiply the digital signals by the correction coefficients based on phase errors between the sampling timings of the NA/D converters digital signals and an ideal sampling timing, respectively.
The window function multiplier may have N coefficient multipliers operable to multiply the digital signals by the predetermined correction coefficients, respectively, and the N coefficient multipliers may correspond to the N A/D converters, respectively, and multiply the digital signals converted by the A/D converters corresponding thereto by the correction coefficients, respectively.
The window function multiplier may have a memory unit operable to store a plurality of correction coefficients supplied in advance, and the window function multiplier may select one of the plurality of correction coefficients one by one for the respective digital signal.
The window function multiplier may calculate the correction coefficients to be multiplied by the respective digital signals based on the sampling timings, and includes a memory unit operable to store the calculated correction coefficients.
The window function multiplier may have N memory units respectively corresponding to N coefficient multipliers, and the N memory units may store the correction coefficients based on phase errors between the sampling timings of the A/D converters corresponding thereto and an ideal sampling timings.
The window function multiplier may multiply the digital signals sampled in an outside of a predetermined time domain by zero.
The FT processor may have an interleaving unit operable to generate a data sequence by arranging the digital signals multiplied by the correction coefficients in a predetermined order.
The FT processor may have an interleaving unit operable to generate a data sequence by arranging the digital signals that the window function multiplier did not multiply by zero in a predetermined order.
The FT processor may perform Fast Fourier Transform (FFT) for the data sequence.
The FT processor may further include: a first FFT processor operable to perform FFT for a sequence of even-numbered data units of the data sequence; a second FFT processor operable to perform FFT for a sequence of odd-numbered data units of the data sequence; and a butterfly operation unit operable to perform a butterfly operation for correcting the digital signals after being subjected to FFT by the first and second FFT processors, based on phase correction coefficients for correcting phase errors between the sampling timings by the N A/D converters and an ideal sampling timing.
The butterfly operation unit may multiply the digital signals after being subjected to FFT by one of the first and second FFT processors by a first phase correction coefficient for correcting the phase errors to perform the butterfly operation.
The butterfly operation unit may multiply the digital signals calculated by the butterfly operation by one of second and third phase correction coefficients that are based on the first phase correction coefficient.
The butterfly operation unit may perform an operation using the first, second and third correction coefficients expressed by the following expressions,
xcex1=exp[jxcfx80xcfx84/Ts]
xcex2=1/(1+xcex1)
xcex2xe2x80x2=xcex1/(1+xcex1)
in a case where the first, second and third phase correction coefficients are xcex1, xcex2, and xcex2xe2x80x2, respectively, where j is an imaginary unit, xcfx84 is the phase error, and T is the ideal sampling timing.
The digitizer apparatus may comprise four A/D converters, wherein the FT processor has four FFT processors operable to perform FFT for the digital data converted by the A/D converters, respectively, the FT processor includes two stages of butterfly operation units operable to perform butterfly operations for correcting the digital signals after being subjected to FFT based on phase correction coefficients for correcting phase errors (xcfx840, xcfx841, xcfx842, xcfx843) between the respective sampling timings of the four A/D converters and an ideal sampling timing, the butterfly operation units at a first stage perform the butterfly operations for (xcfx842xe2x88x92xcfx840) and (xcfx843xe2x88x92xcfx841), and the butterfly operation unit at a second stage performs the butterfly operation for (xcfx841xe2x88x92xcfx840).
The digitizer apparatus may comprise eight A/D converters, wherein the FT processor has eight FFT processors operable to perform FFT for the digital data converted by the A/D converters, respectively, the FT processor includes three stages of butterfly operation units operable to perform butterfly operations for correcting the digital signals after being subjected to FFT based on phase correction coefficients for correcting phase errors (xcfx840, xcfx841, xcfx842, xcfx843, xcfx844, xcfx845, xcfx846, xcfx847) between the respective sampling timings of the eight A/D converters and an ideal sampling timing, the butterfly operation units at a first stage perform the butterfly operations for (xcfx844xe2x88x92xcfx840), (xcfx846xe2x88x92xcfx842), (xcfx845xe2x88x92xcfx841) and (xcfx847xe2x88x92xcfx843), the butterfly operation units at a second stage perform the butterfly operations for (xcfx842xe2x88x92xcfx840) and (xcfx843xe2x88x92xcfx841), and the butterfly operation unit at a third stage performs the butterfly operation for (xcfx841xe2x88x92xcfx840).
According to the second aspect of the present invention, a semiconductor testing apparatus for testing a semiconductor device, comprises: a pattern generator operable to generate a pattern signal and an expected value signal; a waveform shaping unit operable to shape a waveform of the pattern signal generated by the pattern generator; a semiconductor device contact portion, on which the semiconductor device is placed, operable to supply the pattern signal after being shaped by the waveform shaping unit to the semiconductor device and receive an analog signal output from the semiconductor device; a digitizer apparatus operable to convert the analog signal output from the semiconductor device to a digital signal; and a comparator operable to compare the expected value signal output from the pattern generator and the signal output from the digitizer apparatus, wherein the digitizer apparatus includes: NA/D converters operable to convert the analog signal output from the semiconductor device to digital signals at different sampling timings, respectively, where N is an integer equal to or larger than two; a window function multiplier operable to multiply the digital signals by predetermined correction coefficients, respectively; and an FT processor operable to perform Fourier Transform (FT) for the digital signals multiplied by the predetermined correction coefficients, and wherein the window function multiplier multiplies the digital signals by the correction coefficients based on the sampling timings.
The FT processor may include: an interleaving unit operable to generate a data sequence by arranging the digital signals multiplied by the correction coefficients in a predetermined order; a first FFT processor operable to perform FFT for a sequence of even-numbered data units of the data sequence; a second FFT processor operable to perform FFT for a sequence of odd-numbered data units of the data sequence; and a butterfly operation unit operable to perform a butterfly operation for correcting the digital signals after being subjected to FFT, based on phase correction coefficients for correcting phase differences between sampling timings of the N A/D converters and an ideal sampling timing.
The butterfly operation unit may multiply the digital signals after being subjected to FFT by one of the first and second FFT processors by a first phase correction coefficient for correcting the phase errors.
The summary of the invention does not necessarily describe all necessary features of the present invention. The present invention may also be a sub-combination of the features described above. The above and other features and advantages of the present invention will become more apparent from the following description of the embodiments taken in conjunction with the accompanying drawings.